module testMaster;
	
	//parameters
  	parameter DATA_WIDTH = 32;
  	parameter STRB_WIDTH = 4;
	parameter ADDR_WIDTH = 10;
	parameter WR1_RD0	 = 1;
	parameter SLV_SEL 	 = 2;
	parameter DEPTH 	 = 10;
	parameter CMD_LENGTH = DATA_WIDTH + ADDR_WIDTH + WR1_RD0 + SLV_SEL;
	
  	wire [ADDR_WIDTH-1:0]	PADDR;
  wire [SLV_SEL-1:0]					PSELx;
   
    //INPUT
    reg 						PCLK; 
    reg 						PRESETn;
    wire 						PREADY;
  	wire						PENABLE;
  	wire	 [STRB_WIDTH-1:0]	PSTRB;
    wire 						PSLVERR;
    wire 	 [DATA_WIDTH-1:0] 	PRDATA;
  	wire 	 [DATA_WIDTH-1:0]   PWDATA;
    reg 						fifoFull;
    reg 						fifoEmpty;
    wire 	 [CMD_LENGTH-1:0]	CMD;
	//fifo signal Declarations
    wire						fifoWriteEnable;
    wire						fifoReadEnable;
	wire 						full;
	wire						empty;
	wire	[CMD_LENGTH-1: 0]	dataRead;
    //output reg 	[CMD_LENGTH-1: 0]	cmd;
	reg							clk;
	reg							resetn;
	reg							writeEnable;
	reg							readEnable;
	reg		[CMD_LENGTH-1:0]	dataWrite;
    reg 	[DATA_WIDTH-1:0]	dataSeed;
    reg		[ADDR_WIDTH-1:0]	addrSeed;
    integer 					i;
    //reg [3:0] cell;
	
  	initial begin
		clk = 0;
		forever #5 clk = ~clk;
	end

	/*fifo fifoWrite(	clk,
				resetn,
				full,
				empty,
				writeEnable,
                (readEnable || fifoReadEnable),
				dataWrite,
				dataRead);*/

    apb DUT(.PCLK				(clk),
            .PRESETn			(resetn),
            .PADDR				(PADDR),
            .PPROT				(1'b0),
            .PSELx				(PSELx),
            .PENABLE			(PENABLE),
            .PSTRB				(PSTRB),
            .PWRITE				(PWRITE),
            .PWDATA				(PWDATA),
            .PREADY				(PREADY),
            .PRDATA				(PRDATA),
            .PSLVERR			(PSLVERR),
            .fifoWriteEnable	(fifoWriteEnable),
            .fifoReadEnable		(fifoReadEnable),
            .fifoFull			(fifoFull),
            .fifoEmpty			(fifoEmpty),
            .CMD				(dataWrite));
  
  slaveSel SS(.clk		(clk),
              .resetn	(resetn),
              .PADDR	(PADDR),
              .PPROT 	(1'b0),
              .PSEL	(PSELx),
              .PENABLE	(PENABLE),
              .PWRITE	(PWRITE),
              .PWDATA	(PWDATA),
              .PSTRB	(PSTRB),
              .PREADY	(PREADY),
              .PRDATA	(PRDATA),
              .PSLVERR	(PSLVERR));
		//	    CMD);
  
	/*fifo fifoRead(	clk,
				resetn,
				full,
				empty,
				writeEnable,
				readEnable,
				dataWrite,
				dataRead); */
	
	task reset;
	begin
		//cell = 1'b1;
		addrSeed = {ADDR_WIDTH{1'b0}};
		dataSeed = {DATA_WIDTH{1'b1}};
		resetn = 1;
		#2 resetn = 0;
		#8 resetn = 1;
	end
	endtask

	task write;
	begin
		writeEnable = 1;
		readEnable = 0;
		addrSeed = addrSeed + 10;
		dataSeed = dataSeed - 10;
		//addrSeed = $random(dataSeed);
      	//fifoEmpty = 1'b0;
		dataWrite = {dataSeed,addrSeed,1'b1,2'b00};
		//cell = cell + 1;
	end
	endtask

	task read;
	begin
		writeEnable = 0;
		readEnable = 1;
		//if(cell > 0) cell = cell - 1;
		//addrSeed = addrSeed + 10;
		//dataSeed = dataSeed - 10;
		//addrSeed = $random(dataSeed);
      dataWrite = {dataSeed,addrSeed,1'b0,2'b00};
	end
	endtask

	//stimulus
	initial begin
		reset;
      /*for(i=0; i< DEPTH; i=i+1) begin
			#10 write;
		end*/
		/*
		for(i=0; i< DEPTH; i=i+1) begin
			#10 read;
		end
		
		for(i=0; i< DEPTH; i=i+1) begin
			#10 read;
			#10 write;
			#10 write;
		end

		for(i=0; i< DEPTH; i=i+1) begin
			#10 read;
		end
		*/
      #10 
      write;
      fifoEmpty = 1'b0;
      
      #10 
      fifoEmpty = 1'b1;
      
      #20 
      fifoEmpty = 1'b0;
      read;
      
      #10 
      fifoEmpty = 1'b1;
      //dataRead <= {}
		#60 $finish;
	end
	initial begin
		$dumpfile("testwave.vcd");
		$dumpvars;
	end
endmodule
